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US Patent 11417658 NAND string utilizing floating body memory cell

Patent 11417658 was granted and assigned to Zeno Semiconductor on August, 2022 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Zeno Semiconductor
Zeno Semiconductor
Current Assignee
Zeno Semiconductor
Zeno Semiconductor
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11417658
Date of Patent
August 16, 2022
Patent Application Number
17219564
Date Filed
March 31, 2021
Patent Citations
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US Patent 10181471 Memory cell comprising first and second transistors and methods of operating
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US Patent 10644001 Semiconductor memory device having an electrically floating body transistor
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US Patent 10644002 Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle
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US Patent 10707209 Asymmetric semiconductor memory device having electrically floating body transistor
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US Patent 10734076 Memory cells, memory cell arrays, methods of using and methods of making
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US Patent 10748904 Method of maintaining the state of semiconductor memory having electrically floating body transistor
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US Patent 10797055 Memory cell comprising first and second transistors and methods of operating
‌
US Patent 10804276 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
...
Patent Citations Received
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US Patent 11882684 Memory device comprising an electrically floating body transistor
0
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US Patent 11769832 Memory device comprising an electrically floating body transistor and methods of using
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US Patent 12094526 Memory device comprising electrically floating body transistor
0
0
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US Patent 11943937 Memory cell and memory array select transistor
0
Patent Primary Examiner
‌
Huan Hoang
CPC Code
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H01L 27/1157
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H01L 27/11524
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G11C 5/063
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G11C 11/4096
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G11C 11/4099
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H01L 27/10897
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G11C 16/0416
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G11C 16/0483
...

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

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