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US Patent 11387649 Operating circuit having ESD protection function

Patent 11387649 was granted and assigned to Vanguard International Semiconductor Corporation on July, 2022 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Vanguard International Semiconductor Corporation
Vanguard International Semiconductor Corporation
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Current Assignee
Vanguard International Semiconductor Corporation
Vanguard International Semiconductor Corporation
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
113876490
Patent Inventor Names
Chih-Hsuan Lin0
Ching-Ho Li0
Chun-Chih Chen0
Kai-Chieh Hsu0
Li-Fan Chen0
Shao-Chang Huang0
Ting-You Lin0
Yu-Kai Wang0
Date of Patent
July 12, 2022
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Patent Application Number
165675910
Date Filed
September 11, 2019
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Patent Citations
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US Patent 10523002 Electrostatic discharge protection circuit
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US Patent 10714934 Electrostatic discharge protection device, detection circuit and protection method thereof
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US Patent 10177135 Integrated circuit and electrostatic discharge protection circuit thereof
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US Patent 10164627 Power-on control circuit
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US Patent 11088541 Integrated circuit and electrostatic discharge protection circuit thereof
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US Patent 10056897 Power-on control circuit with state-recovery mechanism and operating circuit utilizing the same
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Patent Primary Examiner
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Thienvu V Tran
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CPC Code
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H03K 17/0822
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H02H 9/046
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H02H 9/04
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H02H 9/041
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An operating circuit is provided. A first N-type transistor determines whether to create an open circuit between a core circuit and a ground terminal according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific node according to the first detection signal.

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