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US Patent 11368132 Low delay, low power and high linearity class-D modulation loop

Patent 11368132 was granted and assigned to Synaptics on June, 2022 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Synaptics
Synaptics
Current Assignee
Synaptics
Synaptics
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11368132
Patent Inventor Names
Yunfu Zhang0
Lorenzo Crespi0
Dan Shen0
Date of Patent
June 21, 2022
Patent Application Number
17119978
Date Filed
December 11, 2020
Patent Citations
‌
US Patent 10084369 Error amplifying and frequency compensating circuits and methods
Patent Primary Examiner
‌
Hieu P Nguyen
CPC Code
‌
H03F 1/26
‌
H03F 1/32
‌
H03F 3/2175
‌
H03F 2200/03
‌
H03F 3/68
‌
H03F 3/187
‌
H03F 3/217
‌
H03F 1/02
...

Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

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