Patent attributes
The application describes a transimpedance amplifier circuit having a first circuit branch extending between first and second supply nodes. An input NMOS transistor is located in the first circuit branch, with its drain terminal coupled to the first supply node via a load resistor, its source terminal coupled to the second supply node and its gate terminal coupled to an input node for receiving an input signal. The circuit includes a PMOS transistor having its source terminal coupled to a third supply node, its drain terminal coupled to the first circuit branch, at a node in a part of the first circuit branch extending from the drain terminal of the input transistor to the load resistor, and its gate terminal coupled to the input node. A drain current of the PMOS transistor contributes a proportion but not all of a drain current for input NMOS transistor.
