SBIR/STTR Award attributes
Highly-segmented detectors with pixels smaller than 50 microns present a significant challenge for integration with arrays of thinned integrated circuits (< 50 microns, with areas of ~2x2 cm^2). Since up to 5-10 connections per pixel between the readout high-density CMOS circuits and the detector may be required, bump bonding may not be up to the task. The goal of this proposal is to demonstrate reliable, readily-manufacturable three-dimensional (3D) high density chip interconnect technologies to integrate high resistivity silicon detectors to CMOS front-end readout integrated circuits (ROIC) for the manufacture of advanced scientific instrumentation. A 3D three-dimensional integrated circuit is composed of multiple tiers of integrated electronics and sensors integrated vertically by hybrid bonding, thinning and insertion of through-silicon-vias (TSV). The technologies associated with three 3D integrated circuits can provide new capabilities for particle physics experiments and x-ray imaging. These include finer pixel pitch, lower interconnect capacitance, the ability to separate analog and digital functions, and better power distribution and connectivity. To accomplish the objective, two approaches will be explored and short select one method for high volume manufacturing using larger wafer sizes (>200 mm wafers). Option 1: Sequential chip to wafer (C2W) bonding: Direct ROIC chip attachment into sensor wafer can be accomplished by leveraging Cactus Materials Inc’s (“Cactus”) state- of-the-art wafer bonding technology at room temperature and annealed below 250C. In this method, known good chips (KGC) from ROIC wafer can be picked and directly bonded to sensor wafer one by one. However each chip must be individually handled, and there is a per-placement bond efficiency which must be very high (>99%) to insure good yields on a multi-chip array. Option 2: Wafer to wafer (W2W) bonding of ROIC wafer (comprising of chips) to sensor wafer: All chips on wafer level can be bonded to sensor wafer directly using Cactus’s W2W bonding technology. This technique can provide much higher bond yields than chip-to-wafer, is simpler and much less costly. However, all ROIC chips within the bond field must be functional or the whole array must be thrown away. To reduce the risk, W2W bonding can be combined with “edgeless” sensors to provide flexibility in array fabrication. These approaches are based on vertical integration by through silicon vias (TSVs) which have potential advantages over the current bump-bonded approach.
