List of VeriSilicon Holdings patents

List of VeriSilicon Holdings patents

List of Bombardier Inc. patents

List of PuraCath Medical, Inc. patents

List of Banner Health patents

List of Techstars Class 60 - Barclays NYC 2015 Summer companies

Investors in AppOnboard

Patents where

Current Assignee

Name

is

VeriSilicon Holdings

	Name	Description	Patent Applicant	Current Assignee	Inventor	Patent Jurisdiction	Patent Number	Date of Patent
	‌ US Patent 7418578 Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups	Patent 7418578 was granted and assigned to VeriSilicon Holdings on August, 2008 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7418578	August 26, 2008
	‌ US Patent 7275149 System and method for evaluating and efficiently executing conditional instructions	Patent 7275149 was granted and assigned to VeriSilicon Holdings on September, 2007 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7275149	September 25, 2007
	‌ US Patent 7272704 Hardware looping mechanism and method for efficient execution of discontinuity instructions	Patent 7272704 was granted and assigned to VeriSilicon Holdings on September, 2007 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7272704	September 18, 2007
	‌ US Patent 7426710 Standard cell library having cell drive strengths selected according to delay	Patent 7426710 was granted and assigned to VeriSilicon Holdings on September, 2008 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7426710	September 16, 2008
	‌ US Patent 7254802 Standard cell library having cell drive strengths selected according to delay	Patent 7254802 was granted and assigned to VeriSilicon Holdings on August, 2007 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7254802	August 7, 2007
	‌ US Patent 7231510 Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof	Patent 7231510 was granted and assigned to VeriSilicon Holdings on June, 2007 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7231510	June 12, 2007
	‌ US Patent 7574468 Digital signal processor having inverse discrete cosine transform engine for video decoding and partitioned distributed arithmetic multiply/accumulate unit therefor	Patent 7574468 was granted and assigned to VeriSilicon Holdings on August, 2009 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7574468	August 11, 2009
	‌ US Patent 8095781 Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof	Patent 8095781 was granted and assigned to VeriSilicon Holdings on January, 2012 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	8095781	January 10, 2012
	‌ US Patent 7360117 In-circuit emulation debugger and method of operation thereof	Patent 7360117 was granted and assigned to VeriSilicon Holdings on April, 2008 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7360117	April 15, 2008
	‌ US Patent 7251721 Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers through each corresponding register of said register sets as instructions move through the pipeline	Patent 7251721 was granted and assigned to VeriSilicon Holdings on July, 2007 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7251721	July 31, 2007
	‌ US Patent 7434036 System and method for executing software program instructions using a condition specified within a conditional execution instruction	Patent 7434036 was granted and assigned to VeriSilicon Holdings on October, 2008 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7434036	October 7, 2008
	‌ US Patent 7185294 Standard cell library having globally scalable transistor channel length	Patent 7185294 was granted and assigned to VeriSilicon Holdings on February, 2007 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7185294	February 27, 2007
	‌ US Patent 7299343 System and method for cooperative execution of multiple branching instructions in a processor	Patent 7299343 was granted and assigned to VeriSilicon Holdings on November, 2007 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	7299343	November 20, 2007
	‌ US Patent 8279977 MIMO signal detector, a method of detecting MIMO signals and a MIMO receiver	Patent 8279977 was granted and assigned to VeriSilicon Holdings on October, 2012 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	8279977	October 2, 2012
	‌ US Patent 8516605 Electronic device and software interlocking security system	Patent 8516605 was granted and assigned to VeriSilicon Holdings on August, 2013 by the United States Patent and Trademark Office.		VeriSilicon Holdings		United States Patent and Trademark Office	8516605	August 20, 2013

15 results

0 selected

15 results

0 selected