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US Patent 7910432 Non-volatile semiconductor storage device and method of manufacturing the same

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Contents

Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7910432
Patent Inventor Names
Ryota Katsumata0
Hiroyasu Tanaka0
Masaru Kidoh0
Masaru Kito0
Yasuyuki Matsuoka0
Yoshiaki Fukuzumi0
Hideaki Aochi0
Date of Patent
March 22, 2011
Patent Application Number
12393509
Date Filed
February 26, 2009
Patent Citations Received
‌
US Patent 12136562 3D semiconductor device and structure with single-crystal layers
0
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US Patent 12016181 3D semiconductor device and structure with logic and memory
0
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US Patent 12027518 3D semiconductor devices and structures with metal layers
0
0
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US Patent 12068187 3D semiconductor device and structure with bonding and DRAM memory cells
0
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US Patent 12080743 Multilevel semiconductor device and structure with image sensors and wafer bonding
0
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US Patent 12094829 3D semiconductor device and structure
0
‌
US Patent 12094892 3D micro display device and structure
0
...
Patent Primary Examiner
‌
Julio J Maldonado
Patent abstract

Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.

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