Patent attributes
The present invention provides an integrated semiconductor memory device comprising: a semiconductor substrate; a plurality of active area lines formed in said semiconductor substrate, each of which active area lines includes a plurality of memory cell selection transistors having a respective wordline contact, bitline contact, and node contact; a plurality of filled insulation trenches arranged between said active area lines; a plurality of rewiring stripes each of which rewires an associated node contact of a memory cell selection transistor from an active area line to above a neighboring filled insulation trench so as to form a respective rewired node contact; a plurality of bitlines being aligned with and running above said active area lines which bitlines are connected to the bitline contacts of the memory cell selection transistors of the respective active area lines; a plurality of wordlines running perpendicular to said bitlines which are connected to the wordline contacts of the memory cell selection transistors of corresponding active area lines; and a plurality of memory cell capacitors each of which is connected to a respective rewired node contact of an associated memory cell selection transistor. The present invention also provides a corresponding manufacturing method for an integrated semiconductor memory device and a memory cell.
