Patent attributes
An integrated semiconductor memory device includes a clock terminal that applies an external clock signal. Read and write accesses are controlled synchronously with the external clock signal. A frequency detector is connected to the clock terminal to detect the frequency of the external clock signal. The frequency detector circuit generates a control signal in a manner dependent on the frequency of the external clock signal, the control signal being used to drive a controllable voltage generator, which generates a level of an internal supply voltage in a manner dependent on the control signal, from which supply voltage further control and supply voltages are derived. The integrated semiconductor memory device makes it possible to adapt the level of internally generated voltages of the integrated semiconductor memory device to the frequency of the external clock signal.
