Patent attributes
A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter, and outputs for providing the bits of the output pointer. The reference signal comprises an information regarding a read latency to be adjusted utilizing the output pointer, the at least one counter provides an m-bit counter reading signal comprising a current counter reading, and the decoder arrangement comprises a plurality of decoder devices each comparing the current counter reading signal with a reference value which is associated with a respective of the decoder devices. Each decoder device provides one bit of the output pointer on the basis of the comparing.
