US Patent 7349254 Charge-trapping memory device and methods for its manufacturing and operation

A charge-trapping memory device includes an array of non-volatile memory cells. The array has at least a first sector and a second sector. Each sector includes a multiplicity of memory cells. Each memory cell is adapted to trap an amount of charge indicative of a programming state. A control circuit is operationally connected to the array and is adapted to access a memory cell of the array by means of storing charge in or removing charge from the memory cell. A disturb detection circuit is operationally connected to the array or the control circuit and is adapted to detect a disturbance level of the first sector based on a disturbance caused by accessing at least one memory cell of the second sector. A disturb leveling circuit is operationally connected to the array and the disturb detection circuit and is adapted to backup the programming state of memory cells of the first sector if the detected disturbance level exceeds a predefined threshold.