US Patent 7260734 Method and circuit for transmitting data between systems having different clock speeds

In order to carry out an equidistant data transfer between clock domains having different clock rates, a combination of a counter (1) and a finite state machine (2) is proposed. Said counter (1) continuously counts off the clock cycles of the faster clock (CLK2, while the finite state machine (2) monitors the clock edges of the slower clock (CLK1) and an enabling signal (EN) for the data transfer with the faster clock (CLK2) is produced according to the count of the counter (1).