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US Patent 7233969 Method and apparatus for a parallel correlator and applications thereof

Patent 7233969 was granted and assigned to ParkerVision (company) on June, 2007 by the United States Patent and Trademark Office.

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Patent
Patent
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Patent attributes

Current Assignee
ParkerVision (company)
ParkerVision (company)
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
72339690
Patent Inventor Names
David F. Sorrells0
Gregory S. Rawlins0
Michael W. Rawlins0
Date of Patent
June 19, 2007
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Patent Application Number
111078610
Date Filed
April 18, 2005
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Patent Primary Examiner
‌
D. H. Malzahn
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Patent abstract

A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0–XM−) with encoding coefficients (C0–CM−1), wherein each of (X0–XM−1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, X0 is multiplied by each state (C0(0) through C0(k−1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k−1). This is repeating for data bits (X1–XM−1) and corresponding coefficients (C1–CM−1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated. The final layer of results includes a separate correlation output for each possible state of the complete set of coefficients (C0–CM−1). The final layer of results is compared to identify a most likely code encoded on said data word. In an embodiment, the summations are pruned to exclude summations that would result in invalid combinations of the encoding coefficients (C0–CM−1). In an embodiment, substantially the same hardware is utilized for processing in-phase and quadrature phase components of the data word (X0–XM−1). In an embodiment, the coefficients (C0–CM−1) represent real numbers. In an alternative embodiment, the coefficients (C0–CM−1) represent complex numbers. In an embodiment, the coefficients (C0–CM−1) are represented with a single bit. Alternatively, the coefficients (C0–CM−1) are represented with multiple bits (e.g., magnitude). In an embodiment, the coefficients (C0–CM−1) represent a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.

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