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US Patent 12136671 Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion

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Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Alexander Reznicek0

Choonghyun Lee0

Pouya Hashemi0

Jingyun Zhang0

Takashi Ando0

Date of Patent

November 5, 2024

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Patent Application Number

175668750

Date Filed

December 31, 2021

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Patent Citations

US Patent 8637871 Asymmetric hetero-structure FET and method of manufacture

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US Patent 8901659 Tapered nanowire structure with reduced off current

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US Patent 9287360 III-V nanowire FET with compositionally-graded channel and wide-bandgap core

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US Patent 9620590 Nanosheet channel-to-source and drain isolation

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US Patent 9640666 Integrated circuit employing variable thickness film

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US Patent 9741811 Integrated circuit devices including source/drain extension regions and methods of forming the same

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US Patent 10014390 Inner spacer formation for nanosheet field-effect transistors with tall suspensions

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US Patent 10403739 Method for fabricating semiconductor device

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Patent Primary Examiner

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CPC Code

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Patent abstract

Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

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