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US Patent 12136566 Semiconductor device and method of manufacture

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Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
121365660
Patent Inventor Names
Po-Nan Yeh0
Kuo-Bin Huang0
Liang-Yin Chen0
Chia-Cheng Chen0
U-Ting Chiu0
Yu-Shih Wang0
Ming-Hsi Yeh0
Chun-Neng Lin0
Date of Patent
November 5, 2024
0
Patent Application Number
179693960
Date Filed
October 19, 2022
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Patent Citations
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US Patent 9236267 Cut-mask patterning process for fin-like field effect transistor (FinFET) device
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US Patent 9236300 Contact plugs in SRAM cells and the method of forming the same
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US Patent 9406804 FinFETs with contact-all-around
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US Patent 9443769 Wrap-around contact
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US Patent 9520482 Method of cutting metal gate
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US Patent 9548366 Self aligned contact scheme
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US Patent 9831183 Contact structure and method of forming
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
0
...
Patent Primary Examiner
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Shahed Ahmed
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CPC Code
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H01L 2221/101
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H01L 23/528
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H01L 21/76814
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H01L 21/76831
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H01L 23/5329
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H01L 23/5226
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H01L 21/76829
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H01L 21/76804
0
...
Patent abstract

Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

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