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US Patent 12132115 Semiconductor device structure with dielectric stressor

Patent 12132115 was granted and assigned to Taiwan Semiconductor Manufacturing Company on October, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
121321150
Patent Inventor Names
Chih-Hao Wang0
Guan-Lin Chen0
Kuo-Cheng Chiang0
Shi-Ning Ju0
Date of Patent
October 29, 2024
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Patent Application Number
178704260
Date Filed
July 21, 2022
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Patent Citations
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US Patent 9502265 Vertical gate all around (VGAA) transistors and methods of forming the same
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US Patent 9520482 Method of cutting metal gate
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US Patent 9536738 Vertical gate all around (VGAA) devices and methods of manufacturing the same
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 10332803 Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming
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US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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US Patent 9209247 Self-aligned wrapped-around structure
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US Patent 9236267 Cut-mask patterning process for fin-like field effect transistor (FinFET) device
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...
Patent Primary Examiner
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Edward Chin
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CPC Code
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H01L 29/0649
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H01L 21/02488
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H01L 29/0673
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H01L 29/42392
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Patent abstract

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

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