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US Patent 12119404 Gate all around structure with additional silicon layer and method for forming the same

Patent 12119404 was granted and assigned to Taiwan Semiconductor Manufacturing Company on October, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
121194040
Patent Inventor Names
Chun-Hsiung Lin0
Chih-Hao Wang0
Chen-Han Wang0
Pei-Hsun Wang0
Date of Patent
October 15, 2024
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Patent Application Number
183440570
Date Filed
June 29, 2023
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Patent Citations
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US Patent 9412828 Aligned gate-all-around structure
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US Patent 9472618 Nanowire field effect transistor device having a replacement gate
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US Patent 9502265 Vertical gate all around (VGAA) transistors and methods of forming the same
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US Patent 9520482 Method of cutting metal gate
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US Patent 9536738 Vertical gate all around (VGAA) devices and methods of manufacturing the same
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US Patent 9570551 Replacement III-V or germanium nanowires by unilateral confined epitaxial growth
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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...
Patent Primary Examiner
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John P. Dulka
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CPC Code
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B82Y 10/00
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H01L 29/785
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H01L 21/02532
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H01L 21/02554
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H01L 21/02603
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H01L 29/0669
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H01L 29/0847
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H01L 29/66795
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...
Patent abstract

Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

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