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US Patent 12119391 Fin-based semiconductor device structure including self-aligned contacts and method for forming the same

Patent 12119391 was granted and assigned to Taiwan Semiconductor Manufacturing Company on October, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
121193910
Patent Inventor Names
Kuan-Lun Cheng0
Mao-Lin Huang0
Kuo-Cheng Chiang0
Chih-Hao Wang0
Lung-Kun Chu0
Jia-Ni Yu0
Chung-Wei Hsu0
Chun-Fu Lu0
Date of Patent
October 15, 2024
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Patent Application Number
180683880
Date Filed
December 19, 2022
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Patent Citations
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US Patent 9472618 Nanowire field effect transistor device having a replacement gate
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US Patent 9502265 Vertical gate all around (VGAA) transistors and methods of forming the same
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US Patent 9520482 Method of cutting metal gate
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US Patent 9536738 Vertical gate all around (VGAA) devices and methods of manufacturing the same
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 11563109 Semiconductor device structure and method for forming the same
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US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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US Patent 9209247 Self-aligned wrapped-around structure
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...
Patent Primary Examiner
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Changhyun Yi
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CPC Code
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H01L 29/66545
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H01L 29/78696
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H01L 29/42376
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H01L 29/0847
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H01L 29/401
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H01L 29/66795
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H01L 21/823431
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H01L 29/0673
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Patent abstract

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.

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