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US Patent 12069856 Methods of forming electronic devices using materials removable at different temperatures

Patent 12069856 was granted and assigned to Micron Technology on August, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Micron Technology
Micron Technology
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Current Assignee
Micron Technology
Micron Technology
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120698560
Patent Inventor Names
Chandra S. Tiwari0
Kunal Shrotri0
Date of Patent
August 20, 2024
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Patent Application Number
180472140
Date Filed
October 17, 2022
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Patent Citations
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US Patent 9431416 Vertical-type nonvolatile memory device and method of manufacturing the same
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US Patent 9640423 Integrated circuits and methods for their fabrication
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US Patent 9640531 Semiconductor device, structure and methods
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US Patent 9666590 High stack 3D memory and method of making
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US Patent 9735256 Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features
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US Patent 10014292 3D semiconductor device and structure
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US Patent 10115723 Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods
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US Patent 10147634 Techniques for trench isolation using flowable dielectric materials
0
...
Patent Primary Examiner
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Allison Bernstein
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Patent abstract

A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

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