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US Patent 11942513 Semiconductor structure and method of fabricating the semiconductor structure

Patent 11942513 was granted and assigned to Taiwan Semiconductor Manufacturing Company on March, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
119425130
Patent Inventor Names
Shi Ning Ju0
Guan-Lin Chen0
Jui-Chien Huang0
Chih-Hao Wang0
Kuo-Cheng Chiang0
Date of Patent
March 26, 2024
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Patent Application Number
175719410
Date Filed
January 10, 2022
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Patent Citations
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US Patent 9502265 Vertical gate all around (VGAA) transistors and methods of forming the same
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US Patent 9520482 Method of cutting metal gate
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US Patent 9536738 Vertical gate all around (VGAA) devices and methods of manufacturing the same
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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US Patent 9741811 Integrated circuit devices including source/drain extension regions and methods of forming the same
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US Patent 10535733 Method of forming a nanosheet transistor
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US Patent 11222949 Semiconductor devices and methods of manufacturing the same
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...
Patent Primary Examiner
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Dao H Nguyen
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CPC Code
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H01L 29/785
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H01L 21/02532
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H01L 21/30604
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H01L 21/26513
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H01L 29/6656
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H01L 29/42392
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H01L 29/1037
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H01L 29/0847
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Patent abstract

The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

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