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US Patent 11923361 Semiconductor device with isolation structure

Patent 11923361 was granted and assigned to Taiwan Semiconductor Manufacturing Company on March, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
119233610
Patent Inventor Names
Shi-Ning Ju0
Chih-Hao Wang0
Kuo-Cheng Chiang0
Kuan-Lun Cheng0
Date of Patent
March 5, 2024
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Patent Application Number
178577400
Date Filed
July 5, 2022
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Patent Citations
‌
US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors
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US Patent 10535733 Method of forming a nanosheet transistor
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US Patent 10573755 Nanosheet FET with box isolation on substrate
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US Patent 9209247 Self-aligned wrapped-around structure
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US Patent 9236267 Cut-mask patterning process for fin-like field effect transistor (FinFET) device
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US Patent 9412817 Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
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US Patent 9412828 Aligned gate-all-around structure
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...
Patent Primary Examiner
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Jonathan Han
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CPC Code
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H01L 27/0924
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H01L 29/66772
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H01L 29/78654
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B82Y 10/00
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H01L 27/0886
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H01L 21/76224
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H01L 21/823431
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H01L 29/0847
0
...
Patent abstract

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.

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