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US Patent 11854803 Gate spacer patterning
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Patent
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Date Filed
July 9, 2021
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Date of Patent
December 26, 2023
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Patent Application Number
17371936
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Patent Citations
US Patent 9947804 Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
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US Patent 10418272 Methods, apparatus, and system for a semiconductor device comprising gates with short heights
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US Patent 10504794 Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor
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US Patent 10629707 FinFET structure with bulbous upper insulative cap portion to protect gate height, and related method
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US Patent 10600885 Vertical fin field effect transistor devices with self-aligned source and drain junctions
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US Patent 11600713 Semiconductor device and method
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US Patent 8980701 Method of forming semiconductor device
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US Patent 9899515 Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain
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Patent Inventor Names
Antony Premkumar Peter
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Pierre Morin
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Boon Teik Chan
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11854803
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Patent Primary Examiner
Farun Lu
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CPC Code
H01L 21/0228
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H01L 21/3212
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H01L 21/823431
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H01L 21/823468
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H01L 21/02274
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H01L 29/6681
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H01L 29/6653
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H01L 21/02282
0
H01L 21/02636
0
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