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US Patent 11835999 Controller which adjusts clock frequency based on received symbol rate

Overview Structured Data Issues Contributors

Is a

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Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Bar Shapira0

Ariel Almog0

Thomas Kernen0

Natan Manevich0

Dotan David Levi0

Date of Patent

December 5, 2023

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Patent Application Number

175781150

Date Filed

January 18, 2022

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Patent Citations

US Patent 7623552 System and method for time synchronizing nodes in an automotive network using input capture

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US Patent 10778361 Stream synchronization

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US Patent 10778406 Synthesized clock synchronization between networks devices

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US Patent 10841243 NIC with programmable pipeline

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US Patent 10879910 Method and apparatus for locking a transmitter oscillator to a reference clock signal in a frequency domain

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US Patent 10887077 Method and apparatus for a one bit per symbol timing recovery phase detector

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US Patent 11070224 Method and apparatus for implementing multirate SerDes systems

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US Patent 11070304 Physical hardware clock chaining

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Patent Primary Examiner

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CPC Code

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Patent abstract

A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.

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