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US Patent 11791422 Semiconductor device with fish bone structure and methods of forming the same

Patent 11791422 was granted and assigned to Taiwan Semiconductor Manufacturing Company on October, 2023 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11791422
Patent Inventor Names
Chih-Chuan Yang
Kuo-Hsiu Hsu
Date of Patent
October 17, 2023
Patent Application Number
17739802
Date Filed
May 9, 2022
Patent Citations
‌
US Patent 10199502 Structure of S/D contact and method of making same
‌
US Patent 10290546 Threshold voltage adjustment for a gate-all-around semiconductor structure
‌
US Patent 10475902 Spacers for nanowire-based integrated circuit device and method of fabricating same
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US Patent 11329168 Semiconductor device with fish bone structure and methods of forming the same
‌
US Patent 9887269 Multi-gate device and method of fabrication thereof
‌
US Patent 9818872 Multi-gate device and method of fabrication thereof
‌
US Patent 9899398 Non-volatile memory device having nanocrystal floating gate and method of fabricating same
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US Patent 10032627 Method for forming stacked nanowire transistors
...
Patent Primary Examiner
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Tong-Ho Kim
CPC Code
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H01L 29/66553
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H01L 29/775
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H01L 21/823821
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H01L 21/823878
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H01L 27/0924
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H01L 29/78696
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H01L 21/02603
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H01L 21/28088
...
Patent abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

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