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US Patent 11765878 Semiconductor device including a layer between a source/drain region and a substrate

Patent 11765878 was granted and assigned to Taiwan Semiconductor Manufacturing Company on September, 2023 by the United States Patent and Trademark Office.

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Patent
Patent

Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11765878
Patent Inventor Names
Kam-Tou Sio
Yi-Hsun Chiu
Date of Patent
September 19, 2023
Patent Application Number
17552500
Date Filed
December 16, 2021
Patent Citations
‌
US Patent 9570551 Replacement III-V or germanium nanowires by unilateral confined epitaxial growth
‌
US Patent 10840146 Structures and SRAM bit cells with a buried cross-couple interconnect
Patent Primary Examiner
‌
Changhyun Yi
CPC Code
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H01L 29/785
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H01L 29/78642
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H01L 27/1104
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H01L 29/0673
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H01L 29/0665
‌
H01L 29/7838
‌
H01L 29/66795
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H01L 29/42392
...
Patent abstract

Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.

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