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US Patent 11670590 Chip structure with etch stop layer and method for forming the same

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Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
116705900
Date of Patent
June 6, 2023
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Patent Application Number
174007640
Date Filed
August 12, 2021
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Patent Citations
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US Patent 9548303 FinFET devices with unique fin shape and the fabrication thereof
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US Patent 8796666 MOS devices with strain buffer layer and methods of forming the same
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US Patent 8963258 FinFET with bottom SiGe layer in source/drain
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US Patent 9093530 Fin structure of FinFET
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US Patent 9171929 Strained structure of semiconductor device and method of making the strained structure
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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Patent Primary Examiner
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Thanhha S. Pham
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CPC Code
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H01L 21/76832
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H01L 21/76834
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H01L 21/76829
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H01L 21/76895
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H01L 21/76841
0
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H01L 21/76831
0

A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The chip structure includes a second etch stop layer over the first buffer layer. The chip structure includes a device element over the second etch stop layer.

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