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US Patent 11669379 Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link

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Patent
Patent
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Patent attributes

Patent Applicant
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Current Assignee
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
116693790
Date of Patent
June 6, 2023
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Patent Application Number
177286210
Date Filed
April 25, 2022
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Patent Citations
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US Patent 7355803 Method and apparatus for optimizing hard disc drive and/or recording medium for the same
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US Patent 7168023 Method and apparatus for full rate erasure handling in CDMA
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US Patent 7200770 Restoring access to a failed data storage device in a redundant memory system
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US Patent 7249289 Method of deciding error rate and semiconductor integrated circuit device
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US Patent 7257762 Memory interface with write buffer and encoder
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US Patent 7339759 Recording medium cartridge and recording/reproducing apparatus therefor
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US Patent 7570447 Storage control device and method for detecting write errors to storage media
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US Patent 7636262 Synchronous memory having shared CRC and strobe pin
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Patent Primary Examiner
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Samir W Rizk
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CPC Code
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H03M 13/611
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H03M 13/2906
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H04L 1/0061
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H04L 1/08
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H04L 1/1867
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G06F 3/0619
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G06F 3/064
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G06F 3/0679
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A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

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