US Patent 11556689 Layout of photonic integrated circuits using fixed coordinate grids

Embodiments relate to the layout of photonic integrated circuits using fixed coordinate grids. In some embodiments, a method includes receiving a request to place a first photonic component within a layout of a photonic integrated circuit. Positionings of components within the layout are represented in a design database utilizing a grid with fixed coordinates. The method further includes calculating, by a processor, precise coordinates and snapped coordinates for positioning of the first photonic component. The snapped coordinates have a precision consistent with the fixed coordinate grid and the precise coordinates have a higher precision than the snapped coordinates. The method further includes, in a design database, representing the positioning of the first photonic component utilizing both the precise coordinates and the snapped coordinates.