US Patent 10249377 Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a word line, and a row decoder. A write operation repeats a program loop including a program operation, first and second verify operations. The row decoder applies a first read voltage to the word line in the first and second verify operations. When the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation. When the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation.