US Patent 10091079 Apparatus and method for remotely testing memory-mapped devices of a system-on-chip via an ethernet interface

A chipset including one or more system-on-chips. The chipset includes a memory-mapped device, an Ethernet interface, and a remote management controller. The memory-mapped device includes a test access port and is configured to access a register based on an address of a memory corresponding to the register. The Ethernet interface is configured to receive Ethernet frames transmitted over an Ethernet network. One or more of the Ethernet frames are received from a host device. The one or more of the Ethernet frames are received to test the one or more system-on-chips. The remote management controller is coupled to the test access port. The remote management controller is configured to, based on the one or more of the Ethernet frames, remotely control operation of the memory-mapped device or another device in the one or more system-on-chips, and restrict (a) testing of the one or more system-on-chips or the memory-mapped device, and (b) access by the host device to the register.