SBIR/STTR Award attributes
A significant performance gap exists between the theoretical number of Floating Point Operations (FLOPS) that a HPC machine is capable of sustaining and the number of FLOPS realized by real-world HPC applications. One of the principle reasons for this gap is the parasitic work that computational processes must do to communicate with one another. It has been shown that this communication work can be significantly reduced by using a topology aware mapping of processes to compute nodes. Tools for topology aware process mapping have been developed. However, many existing tools either lack support for dynamic communication patterns, variable network loads, or support legacy FORTRAN applications. The MPI standard defines a mechanism for topology aware process mapping; however, few MPI implementations support this. This work will overcome these limitations by developing an MPI based library that implements the topology aware mapping mechanism defined by the MPI standard. Furthermore, a command line utility will be developed that uses application profile data to estimate application performance on new platforms. In Phase I, a prototype MPI based toolkit along with supporting theory will be developed and demonstrated. In Phase II a production quality toolkit, along with user and system administration documentation will be developed.
