Roman Kashirin

S1 ("Power on Suspend" (POS) in the BIOS), a state in which all processor caches are reset and the processors have stopped executing instructions. However, power to processors and RAM is maintained; devices that are not designated to remain on may be disabled;

S2 is a deeper sleep state than S1, when the CPU is off, but usually not in use;

S3 ("Suspend to RAM" (STR in BIOS, "Standby" in Windows versions up to Windows XP and in some Linux variations, "Sleep" in Windows Vista and Mac OS X, though ACPI specifications refer only to S3 and Sleep) - in this state the RAM continues to be powered and is almost the only component consuming power. Since the state of the operating system and all applications, open documents etc. are stored in RAM, the user can resume work exactly where he left it - the state of RAM when returning from S3 is the same as it was before entering this mode. (The specification states that S3 is quite similar to S2, only slightly more components are disabled in S3.) S3 has two advantages over S4: the computer returns to operating state faster, and, second, if a running program (open documents, etc.) contains sensitive information, that information will not be forced to be written to disk. However, disk caches can be reset to disk to prevent compromising data integrity if the system does not wake up, for example due to a power failure;

S4 ("Hibernation" in Windows, "Safe Sleep" in Mac OS X, also known as "Suspend to disk", although the ACPI specification only mentions the term S4) - in this state all the contents of RAM are stored in non-volatile memory such as the hard disk: state of the operating system, all applications, open documents, etc. This means that after returning from S4, the user can resume work from where it was stopped, similar to the S3 mode. The difference between S4 and S3, apart from the extra time to move the contents of RAM to disk and back, is that a power failure in S3 will cause the computer to lose all data in RAM, including all unsaved documents, whereas the computer in S4 is not affected. S4 is quite different from the other S states and more strongly resembles G2 Soft Off and G3 Mechanical Off. A system in S4 can also be switched to G3 Mechanical Off and still remain in S4, saving state information so that the operating state can be restored after power-up.

• S1 ("Power on Suspend" (POS) in the BIOS), a state in which all processor caches are reset and the processors have stopped executing instructions. However, power to processors and RAM is maintained; devices that are not designated to remain on may be disabled;
• S2 is a deeper sleep state than S1, when the CPU is off, but usually not in use;
• S3 ("Suspend to RAM" (STR in BIOS, "Standby" in Windows versions up to Windows XP and in some Linux variations, "Sleep" in Windows Vista and Mac OS X, though ACPI specifications refer only to S3 and Sleep) - in this state the RAM continues to be powered and is almost the only component consuming power. Since the state of the operating system and all applications, open documents etc. are stored in RAM, the user can resume work exactly where he left it - the state of RAM when returning from S3 is the same as it was before entering this mode. (The specification states that S3 is quite similar to S2, only slightly more components are disabled in S3.) S3 has two advantages over S4: the computer returns to operating state faster, and, second, if a running program (open documents, etc.) contains sensitive information, that information will not be forced to be written to disk. However, disk caches can be reset to disk to prevent compromising data integrity if the system does not wake up, for example due to a power failure;
• S4 ("Hibernation" in Windows, "Safe Sleep" in Mac OS X, also known as "Suspend to disk", although the ACPI specification only mentions the term S4) - in this state all the contents of RAM are stored in non-volatile memory such as the hard disk: state of the operating system, all applications, open documents, etc. This means that after returning from S4, the user can resume work from where it was stopped, similar to the S3 mode. The difference between S4 and S3, apart from the extra time to move the contents of RAM to disk and back, is that a power failure in S3 will cause the computer to lose all data in RAM, including all unsaved documents, whereas the computer in S4 is not affected. S4 is quite different from the other S states and more strongly resembles G2 Soft Off and G3 Mechanical Off. A system in S4 can also be switched to G3 Mechanical Off and still remain in S4, saving state information so that the operating state can be restored after power-up.

CPU states

There are four states (from C0 to C3) of the CPU.

C0 - operational (working) mode.

• C1 (known as Halt) is a state in which the processor does not execute instructions but can immediately return to an operational state. Some processors, Pentium 4 for example, also support Enhanced C1 (C1E) state for lower power consumption.
• C2 (known as Stop-Clock) - A state where the processor is detected by applications, but it takes time to return to operating mode.
• C3 (known as Sleep) - A state in which the processor turns off its own cache, but is ready to move to other states.

Device states

There are four different device states (monitor, modem, bus, network cards, graphics card, disks, floppies, etc) ranging from D0 to D3.

• D0 is a fully operational state, the device is on.
• D1 and D2 - intermediate states, activity is determined by the device.
• D3 - device is off.

Performance states

While a processor or device is operational (C0 and D0, respectively), it may be in one or more performance states. These states depend on the particular implementation. For example, P0 is always the highest performance level; from P1 to Pn the performance level decreases sequentially, to the implementation limit, where n is less than 16.

P-states are also known as SpeedStep in Intel processors, as PowerNow! or Cool'n'Quiet in AMD processors, and as LongHaul in VIA processors.

• P0 maximum performance and frequency
• P1 less than P0, voltage/frequency cutoff
• P2 less than P1, voltage/frequency cutoff
• ...
• Pn less than P(n-1), voltage/frequency trimmed

ACPI (Advanced Configuration and Power Interface) ACPI (Advanced Configuration and Power Interface) is an open industry standard first released in December 1996 and co-developed by HP, Intel, Microsoft, Phoenix, and Toshiba that defines a common interface for hardware discovery, power management, and motherboard and device configuration.

Currently, the latest version of the ACPI specification is version 6.2a, released by the UEFI Forum in September 2017.[1]

Introduction

Introduction

Technical details

Technical details

States

Global states

States

Global states

ACPI (Advanced Configuration and Power Interface) is an open industry standard first released in December 1996 and co-developed by HP, Intel, Microsoft, Phoenix, and Toshiba that defines a common interface for hardware discovery, power management, and motherboard and device configuration.

The 2.0 specification was introduced in September 2000. It applies to a broader range of computers, including enterprise servers, desktops, and laptops. In addition, ACPI 2.0 added support for 64-bit microprocessors for servers, support for various types of memory, PCI and PCI-X devices.

Version 3.0b of the specification was released on October 10, 2006.

Currently, the latest version of the ACPI specification is version 6.2a, released by the UEFI Forum in September 2017.[1]

The purpose of ACPI is to provide an interface between the operating system, the hardware, and the motherboard BIOS.

ACPI has replaced APM (Advanced Power Management) technology.

Introduction

The most famous part of the ACPI standard is power management, which has two significant improvements over previous standards. Firstly, the ACPI concept transfers power control to the operating system (OS). This is in contrast to the previous APM model, where the motherboard BIOS was responsible for power management and the OS power capabilities were severely limited. In the ACPI model, the BIOS provides the operating system with methods for direct detailed hardware control. This gives the OS almost complete control over power consumption.

Another important part of the ACPI specification is to provide power management features on servers and desktops that were previously only available on laptop computers. For example, a system can be put into an extremely low-power state in which only the RAM is powered (or possibly unpowered), but interrupts from some devices (real-time clock, keyboard, modem, etc.) can bring the system from such a state to normal operating mode fairly quickly (i.e. "wake up" the system).

Besides the software interface requirements, ACPI also requires special support from the hardware. Thus, the operating system, motherboard chipset and even the CPU must all have ACPI support.

Today, various versions of ACPI are supported by many operating systems - including all versions of Microsoft Windows since Windows 98, GNU/Linux systems, FreeBSD, OpenBSD, NetBSD, and eComStation.

Technical details

The ACPI interface is organized by putting several tables in a certain area of memory that describe hardware resources and software methods to control them. Each table type has a specific format described in the specification. Besides, the tables that contain device control methods and ACPI event handlers contain AML (ACPI Machine Language) code, which is a machine-independent instruction set presented in a compact form. An operating system that supports ACPI contains an AML interpreter that translates AML instructions into CPU instructions, thus executing methods or event handlers.

Some of these tables store all or part of the static data in the sense that it does not change from run to run of the system. Static data is usually created by the motherboard or BIOS manufacturer and described in a special language, ASL (ACPI Source Language), and then compiled into an AML representation.

Other tables store dynamic data that depends on, for example, the BIOS settings and the motherboard's configuration. These tables are generated by the BIOS during the system boot phase before control is transferred to the OS.

The role of the OS in this model is to move various hardware components from one state (e.g., normal operation) to another state (e.g., low-power mode). The transition from one state to another usually occurs by an event. For example, a drop in CPU core temperature is an event by which the OS can invoke a fan speed reduction method. Another example: a user explicitly told the system to hibernate, saving RAM to disk, and some time later the network administrator turned on the system with the Wake-on-LAN function.

States

Global states

The following basic states of the "system as a whole" are distinguished.

G0 (S0) (Working) - normal operation.

G1 (Suspend, Sleeping, Sleeping Legacy) - machine is shut down, but current system context is preserved, operation can be continued without rebooting. For each device, the "degree of information loss" in the process of falling asleep is defined, as well as where the information should be stored and from where it will be read when waking up, and the time to wake up from one state to another (for example, from sleeping to working state). Four states of sleep are distinguished:

S1 ("Power on Suspend" (POS) in the BIOS), a state in which all processor caches are reset and the processors have stopped executing instructions. However, power to processors and RAM is maintained; devices that are not designated to remain on may be disabled;

S2 is a deeper sleep state than S1, when the CPU is off, but usually not in use;

S3 ("Suspend to RAM" (STR in BIOS, "Standby" in Windows versions up to Windows XP and in some Linux variations, "Sleep" in Windows Vista and Mac OS X, though ACPI specifications refer only to S3 and Sleep) - in this state the RAM continues to be powered and is almost the only component consuming power. Since the state of the operating system and all applications, open documents etc. are stored in RAM, the user can resume work exactly where he left it - the state of RAM when returning from S3 is the same as it was before entering this mode. (The specification states that S3 is quite similar to S2, only slightly more components are disabled in S3.) S3 has two advantages over S4: the computer returns to operating state faster, and, second, if a running program (open documents, etc.) contains sensitive information, that information will not be forced to be written to disk. However, disk caches can be reset to disk to prevent compromising data integrity if the system does not wake up, for example due to a power failure;

S4 ("Hibernation" in Windows, "Safe Sleep" in Mac OS X, also known as "Suspend to disk", although the ACPI specification only mentions the term S4) - in this state all the contents of RAM are stored in non-volatile memory such as the hard disk: state of the operating system, all applications, open documents, etc. This means that after returning from S4, the user can resume work from where it was stopped, similar to the S3 mode. The difference between S4 and S3, apart from the extra time to move the contents of RAM to disk and back, is that a power failure in S3 will cause the computer to lose all data in RAM, including all unsaved documents, whereas the computer in S4 is not affected. S4 is quite different from the other S states and more strongly resembles G2 Soft Off and G3 Mechanical Off. A system in S4 can also be switched to G3 Mechanical Off and still remain in S4, saving state information so that the operating state can be restored after power-up.

G2 (S5) (soft-off) - Soft-off; the system is completely stopped but energized, ready to turn on at any time. System context is lost.

G3 (mechanical off) - mechanical system shutdown; ATX power supply is off.

posted write - write data is immediately accepted by the bridge, and the bridge immediately responds "done", already after that trying to perform a write operation on the slave bus;

write combining - several posted write requests, going in a row by addresses, are combined in the bridge into one "burst" transaction on the slave bus;

prefetching - used in read transactions, means sampling immediately a large range of addresses into the bridge cache by one "burst" transaction, further requests are executed by the bridge itself without operations on the slave bus.

• posted write - write data is immediately accepted by the bridge, and the bridge immediately responds "done", already after that trying to perform a write operation on the slave bus;
• write combining - several posted write requests, going in a row by addresses, are combined in the bridge into one "burst" transaction on the slave bus;
• prefetching - used in read transactions, means sampling immediately a large range of addresses into the bridge cache by one "burst" transaction, further requests are executed by the bridge itself without operations on the slave bus.

Configuration

Configuration

The specification is

Bus frequency 33.33 or 66.66 MHz, synchronous transmission;

Bus bit size is 32 or 64 bits, the bus is multiplexed (address and data are sent over the same lines)

peak throughput for the 32-bit version running at 33.33 MHz is 133 Mbytes/sec;

memory address space - 32 bits (4 bytes);

I/O port address space - 32 bits (4 bytes);

configuration address space (for one function) - 256 bytes;

voltage - 3.3 or 5 V.

Specification

• Bus frequency 33.33 or 66.66 MHz, synchronous transmission;
• Bus bit size is 32 or 64 bits, the bus is multiplexed (address and data are sent over the same lines)
• peak throughput for the 32-bit version running at 33.33 MHz is 133 Mbytes/sec;
• memory address space - 32 bits (4 bytes);
• I/O port address space - 32 bits (4 bytes);
• configuration address space (for one function) - 256 bytes;
• voltage - 3.3 or 5 V.

Creation history

Creation history

In the late 2000s[2] and early 2010s, the PCI interface was gradually superseded by the PCI Express and USB interfaces. On consumer motherboards, the number of PCI connectors decreased,[3] they are installed no more than 1-2, instead of 3-4 or more, used in the early 2000s[4]. 4] Some motherboards (especially compact mATX form factors, etc.) don't have a PCI connector at all[3][4].

Architecture

Architecture

Creation history

In the spring of 1991, Intel completed the development of the first prototype version of the PCI bus. The engineers were tasked with developing an inexpensive, high performance solution that would enable the 486, Pentium, and Pentium Pro processors. In addition, it was necessary to take into account the mistakes made by VESA when designing the VLB bus (the electrical load did not allow to connect more than 3 expansion boards), as well as to implement the autoconfiguration of devices on the example of the Autoconfig protocol for Amiga computers. MCA's marketing mistakes were also taken into account, leading to a "gang of nine" confrontation with EISA.

In 1992 the first version of the PCI bus appeared, Intel announced that it would be an open standard, and formed the PCI Special Interest Group. This gave any developer with an interest in the PCI bus the ability to create PCI bus devices without purchasing a license. The first version of the bus was clocked at 33 MHz, could be 32- or 64-bit, and the devices could handle either 5V or 3.3V signals. Theoretically the bus had a bandwidth of 133 Mbytes/s, but in reality the bandwidth was about 90 Mbytes/s.

In mid-1993, Intel withdrew from VESA and began to take active steps to market the PCI bus. The response to criticism from Usenet and competitors (the bus had many of the same characteristics as the Zorro III, and articles were published about the faulty bus design) was PCI 2.0.

1995 saw the introduction of PCI 2.1 (also called the "parallel PCI bus"), which offered a bus data rate of 66 MHz, with a maximum transfer rate of 533 Mbytes/s (for the 64-bit 66 MHz version). In addition, the bus was already supported at the Windows 95 operating system level (Plug and Play technology). The PCI 2.1 bus version had proven so popular that it was soon ported to platforms with Alpha, MIPS, PowerPC, SPARC, etc. processors.

In 1997, with the development of computer graphics and the AGP bus, PCI bus stopped being used for graphics cards due to new, higher requirements to graphics cards.

In the late 2000s[2] and early 2010s, the PCI interface was gradually superseded by the PCI Express and USB interfaces. On consumer motherboards, the number of PCI connectors decreased,[3] they are installed no more than 1-2, instead of 3-4 or more, used in the early 2000s[4]. 4] Some motherboards (especially compact mATX form factors, etc.) don't have a PCI connector at all[3][4].

Architecture

Originally 32 address/data conductors at 33 MHz. Later versions with 64 conductors (using an additional connector pad) and a frequency of 66 MHz appeared.

The bus is decentralized, there is no master device, any device can be the initiator of the transaction. Arbitration is used to select the initiator with a separate arbitrator logic. Arbitration is "hidden", not time-consuming - the selection of a new initiator takes place during the transaction executed by the previous initiator.

A transaction consists of 1 or 2 address cycles (2 address cycles are used to transfer 64-bit addresses, not supported by all devices, give DMA support on memory over 4 GB) and one or many data cycles. Transaction with many data cycles is called "burst" and is understood as a read/write of consecutive addresses and gives higher speed - one address cycle for several, not each data cycle, and no downtime (to "settle" conductors) between transactions.

Special transaction types are used to address the configuration space of a device.

"Batch" transactions can be temporarily suspended by both devices due to missing data in the buffer or buffer overflow.

Split" transactions are supported when the target device responds with an "in progress" state and the initiator must free the bus for other devices, reacquire it through arbitration, and repeat the transaction. This is done until the target device responds "done". It is used to interface buses with different speeds (PCI itself and Front Side Bus of CPU) and to prevent deadlocks in a scenario with many inter-bus bridges.

Rich cross-bus bridge support. Rich support for cache modes, such as:

posted write - write data is immediately accepted by the bridge, and the bridge immediately responds "done", already after that trying to perform a write operation on the slave bus;

write combining - several posted write requests, going in a row by addresses, are combined in the bridge into one "burst" transaction on the slave bus;

prefetching - used in read transactions, means sampling immediately a large range of addresses into the bridge cache by one "burst" transaction, further requests are executed by the bridge itself without operations on the slave bus.

Interrupts are supported either as Message Signaled Interrupts (new) or in the classic way using INTA-D# guides. Interrupt conductors operate independently of the rest of the bus, and it is possible to share one conductor with many devices.

Configuration

PCI devices are self-configuring (Plug and Play) from the user's point of view. After the computer starts, the system software examines the PCI configuration space of each device connected to the bus and allocates resources.

Each device can claim up to six ranges in the PCI memory address space or in the PCI I/O address space.

In addition, devices can have ROM that contains executable code for x86 or PA-RISC processors, Open Firmware (system software for SPARC and PowerPC-based computers), or an EFI driver.

Interrupts are also configured by the system software (unlike on the ISA bus, where interrupts were configured by switches on the card). Interrupt requests on the PCI bus are made by changing the signal level on one of the IRQ lines, so it is possible to have several devices share the same interrupt request line; normally the system software tries to assign a separate interrupt to each device to maximize performance.

The specification is

Bus frequency 33.33 or 66.66 MHz, synchronous transmission;

Bus bit size is 32 or 64 bits, the bus is multiplexed (address and data are sent over the same lines)

peak throughput for the 32-bit version running at 33.33 MHz is 133 Mbytes/sec;

memory address space - 32 bits (4 bytes);

I/O port address space - 32 bits (4 bytes);

configuration address space (for one function) - 256 bytes;

voltage - 3.3 or 5 V.

Embedded storage

As flash memory increased in capacity and became cheaper, solid state memory began to replace HDDs as the primary long-term memory in computers. To ensure interoperability with legacy technologies, embedded SSDs began to be built with the standardized hard drive designs and the most popular hard drive interface at the time. Thus, 2.5" SATA SSDs were introduced to replace mechanical HDDs.

However, the bulky form factors and slow interface speeds of mechanical hard drives made it impossible to unleash the potential of flash memory. The process of miniaturization of drives began. Initially, they abandoned the design of hard drives, standardizing the small size of mSATA and M.2 SATA designs, but retaining compatibility with the SATA interface. The next step was the abandonment of the slow SATA interface and the transition to the fast PCI Express interface. Thus, NVM Express (NVMe) drives appeared in a variety of designs, of which M.2 NVMe was the most common.

Despite this design, M.2 SATA drives cannot be installed in place of M.2 NVMe drives and M.2 NVMe drives cannot be installed in place of M.2 SATA drives and are not compatible. They can be distinguished externally by the number of notches on the drive board pins and the corresponding key inserts on the mating connector: M.2 SATA has two, while M.2 NVMe has one.

Solid-State Drive (SSD)Solid-State Drive (SSD) is a computer's nonvolatile, nonmechanical storage device based on memory chips, an alternative to hard disk drives (HDD). The most common type of SSD uses NAND flash memory for storing information, but there are variants in which the drive is based on DRAM memory with an additional power source - a battery. In addition to the memory chips the SSD has a host controller.

Market

In 2013, the largest manufacturers of NAND chips were Samsung, Toshiba, Micron and SK-Hynix, SSD controller chips were LSI-SandForce, Marvell, Silicon Motion, Phison and JMicron.

In the same year, Samsung, Toshiba and Micron began to produce drives with 3D-NAND chips, which reduced the cost of devices, especially high-capacity ones.

In Q1 2016, the largest SSD manufacturers were Samsung Electronics (first place, about 40% of the market), SanDisk (12%), Lite-On (Plextor, Lite-On), Kingston, Intel, Micron, HGST.

NAND flash memory for SSDs was produced by SanDisk, Toshiba, Samsung, Intel, Micron. Despite the fact that Toshiba was and is one of the largest manufacturers of NAND chips, the company's share of the SSD market was only 3.9%.

Since 2016. Samsung produces "consumer" SSDs with 3D NAND chips exclusively of its own production

External drives

SSDs first proliferated as standalone storage and transfer devices. They were connected to computers and digital gadgets through a number of standardized external interfaces and were designed so that they could be safely manipulated and transferred between devices by untrained users. All these drives could be divided into two large groups: USB drives ("USB flash drives"), primarily used with computers, and memory cards, primarily used in a variety of electronic gadgets such as digital cameras, phones, etc.

USB drives were perfectly standardized and made it work on any device with that connector. Memory cards had a wide variety of incompatible designs and interfaces. Initially CompactFlash, SmartMedia, Memory Stick, MMC, SD were popular. Until our time, only SD-cards in two form factors have retained a high popularity: standard and miniature (microSD).

Development History

1978 - American company StorageTek developed the first semiconductor storage device of modern type (based on RAM-memory).

1982 - the American company Cray introduced a semiconductor RAM-memory drive for its supercomputers Cray-1 at 100 Mbit/s and Cray X-MP at 320 Mbit/s, with the capacity of 8, 16 or 32 million 64-bit words.

1995 - Israeli company M-Systems introduced the first semiconductor flash memory drive.

2007 - ASUS released EEE PC 701 netbook with 4GB SSD.

2008 - South Korea's Mtron Storage Technology manages to create a 128GB SSD drive with a write speed of 240 MB/s and read speed of 260 MB/s.

There are also hybrid hard drives (SSHD, solid-state hybrid drive), in which NAND memory is used together with magnetic plates. This combination allows to take advantage of the advantages of flash memory (fast random access) while maintaining the low cost of storing large amounts of data. Flash memory is used as a small capacity buffer (e.g. Seagate Momentus XT with 4GB to 8GB) or (less commonly) available as a standalone drive (dual-drive hybrid systems)[source unreported 1011 days].

The main characteristics of SSDs are:

The main characteristics of SSDs are:

Solid state drives include only semiconductor drives. Hard disks and optical disks are not included, even though they are, strictly speaking, solid state. This terminology is the opposite of what is used for lasers; solid state lasers are lasers based on any solid state except semiconductors.

Originally, solid state drives were called "solid state disks" even though no solid state drive is a drive. Nowadays this name is becoming less common.

SSDs are devices that store data in chips instead of rotating metal disks or magnetic tapes. The reason for their emergence reflects the fact that the data processing speed of the processor is much faster than the data writing speed of HDDs. Magnetic disks have dominated the corporate storage segment for decades, during that time (since the 1950s) the storage capacity has increased two hundred thousand times, the speed of processors has also increased dramatically, but the data access speed has changed much less and disks have become the bottleneck. The problem has been solved by solid state drives - they provide much faster data access speeds compared to hard disks. SSDs offer significantly different characteristics than magnetic hard disk drives through the use of flash memory chips.

In 2011, the NVMe (Non-Volatile Memory Express) logical interface was developed to optimize the use of SSDs. Support for NVMe was only added to Windows starting with version 8.1. In Windows 7, hotfix KB2990941 provides support for the protocol. Also, not all motherboards support NVMe, so some SSD models are available in two versions - AHCI and NVMe.

There are also hybrid hard drives (SSHD, solid-state hybrid drive), in which NAND memory is used together with magnetic plates. This combination allows to take advantage of the advantages of flash memory (fast random access) while maintaining the low cost of storing large amounts of data. Flash memory is used as a small capacity buffer (e.g. Seagate Momentus XT with 4GB to 8GB) or (less commonly) available as a standalone drive (dual-drive hybrid systems)[source unreported 1011 days].

Intel Smart Response technology allows SSDs and HDDs to be used together to cache frequently accessed data (files) on the SSD, plus it makes better use of SSHDs. Other manufacturers also have their own technologies for using SSDs to cache data stored in HDDs: Marvell HyperDuo (in Marvell 88SE9130 controller), Adaptec MaxIQ (MaxCache), LSI CacheCade. Of these, only HyperDuo is intended for home use.

The main characteristics of SSDs are:

Fastest data access time: 100 to 1000 times faster than mechanical drives;

high speed, up to several gigabytes per second for randomly placed data;

High IOPS due to high speed and low access time

low cost of performance, the best price-to-performance ratio of any storage device;

high reliability; SSDs give the same level of data retention as other semiconductor devices.

Unlike hard disk drives, the price of SSDs is very much dependent on the available capacity, this is due to the limited density of memory cells and the limited chip size in the chip.

Solid-State Drive (SSD) is a computer's nonvolatile, nonmechanical storage device based on memory chips, an alternative to hard disk drives (HDD). The most common type of SSD uses NAND flash memory for storing information, but there are variants in which the drive is based on DRAM memory with an additional power source - a battery. In addition to the memory chips the SSD has a host controller.

Currently, SSDs are used in both portable (laptops, netbooks, tablets) and desktop computers to improve performance. As of 2016, the best performing SSDs were M.2 SSDs with an NVMe interface, which, with the right connection, could write/read data at up to 3,800 megabytes per second.

Compared to traditional hard disk drives, SSDs are smaller and lighter, silent, many times more resistant to damage (e.g., from being dropped) and have much faster operation speeds. At the same time, they are several times more costly per gigabyte and have a shorter endurance (write endurance).

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