Patent attributes
A test system (1) comprises a system-on-chip with a memory (7) for storing sample data; and a dynamic test engine (4) to control input of dynamic test waveforms including sinusoidal waveforms to an ADC under test (15) and to determine device under test dynamic parameters by analysing the samples. A linear test engine (5) determines device under test (15) static parameters, and controls input of ramp input waveforms to the ADC. A test controller (2) performs finite sate machine control of testing including applying test waveforms, dumping samples to the memory (7), and retrieving static and dynamic results. A DAC (3) generates controlled waveform generation under instructions from the test engines, and an interface (10) communicates with an external host. The components are linked with a bus (11) and are modular. The test system (1) is adapted to re-use the memory (7) for both test sample acquisition, and operation of the device under test (15) is adapted to enable re-use circuits in order to minimize logic overheads and maximize use other than ADC test and measurement. The linear and dynamic test engines (5, 4) perform parallel linear and dynamic testing in which dynamic testing sample acquisition and processing takes place during application of a ramped input for linear testing.
