Patent attributes
A memory device is proposed. The memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a functional element with a programmable resistivity and a unidirectional conduction access element connected in series, a plurality of word lines and a plurality of bit lines, the memory cells of each row being connected to a corresponding word line and the memory cells of each column being connected to a corresponding bit line, means for driving the bit lines to a desired voltage, means for selecting at least one bit line in an operative condition of the memory device, each selected bit line being connected to the means for driving and each deselected bit line being disconnected from the means for driving, and means for selecting a word line in the operative condition, each access element associated with the selected word line and the at least one selected bit line being forward biased and the other access elements being reverse biased; the memory device further includes means for biasing the deselected bit lines in the operative condition to prevent a leakage current of the reverse biased access elements from forward biasing the access elements associated with the selected word line and the deselected bit lines.
