List of EASIC patents

Patents where

Current Assignee

Name

EASIC

Name	Description	Patent Applicant	Current Assignee	Patent Jurisdiction	Patent Number	Date of Patent
‌ US Patent 7157937 Structured integrated circuit device	Patent 7157937 was granted and assigned to EASIC on January, 2007 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7157937	January 2, 2007
‌ US Patent 7098691 Structured integrated circuit device	Patent 7098691 was granted and assigned to EASIC on August, 2006 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7098691	August 29, 2006
‌ US Patent 7463062 Structured integrated circuit device	Patent 7463062 was granted and assigned to EASIC on December, 2008 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7463062	December 9, 2008
‌ US Patent 7105871 Semiconductor device	Patent 7105871 was granted and assigned to EASIC on September, 2006 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7105871	September 12, 2006
‌ US Patent 7068070 Customizable and programmable cell array	Patent 7068070 was granted and assigned to EASIC on June, 2006 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7068070	June 27, 2006
‌ US Patent 8629548 Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node	Patent 8629548 was granted and assigned to EASIC on January, 2014 by the United States Patent and Trademark Office.	EASIC	EASIC	United States Patent and Trademark Office	8629548	January 14, 2014
‌ US Patent 8957398 Via-configurable high-performance logic block involving transistor chains	Patent 8957398 was granted and assigned to EASIC on February, 2015 by the United States Patent and Trademark Office.	EASIC	EASIC	United States Patent and Trademark Office	8957398	February 17, 2015
‌ US Patent 7689960 Programmable via modeling	Patent 7689960 was granted and assigned to EASIC on March, 2010 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7689960	March 30, 2010
‌ US Patent 8735857 Via-configurable high-performance logic block architecture	Patent 8735857 was granted and assigned to EASIC on May, 2014 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	8735857	May 27, 2014
‌ US Patent RE46474 Multiple write during simultaneous memory access of a multi-port memory device	Patent RE46474 was granted and assigned to EASIC on July, 2017 by the United States Patent and Trademark Office.	EASIC	EASIC	United States Patent and Trademark Office	RE46474	July 11, 2017
‌ US Patent 8677306 Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC	Patent 8677306 was granted and assigned to EASIC on March, 2014 by the United States Patent and Trademark Office.	EASIC	EASIC	United States Patent and Trademark Office	8677306	March 18, 2014
‌ US Patent 9024657 Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller	Patent 9024657 was granted and assigned to EASIC on May, 2015 by the United States Patent and Trademark Office.	EASIC	EASIC	United States Patent and Trademark Office	9024657	May 5, 2015
‌ US Patent 8040739 Configurable write policy in a memory system	Patent 8040739 was granted and assigned to EASIC on October, 2011 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	8040739	October 18, 2011
‌ US Patent 9704874 ROM segmented bitline circuit	Patent 9704874 was granted and assigned to EASIC on July, 2017 by the United States Patent and Trademark Office.	EASIC	EASIC	United States Patent and Trademark Office	9704874	July 11, 2017
‌ US Patent 7514959 Structured integrated circuit device	Patent 7514959 was granted and assigned to EASIC on April, 2009 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7514959	April 7, 2009
‌ US Patent 7759971 Single via structured IC device	Patent 7759971 was granted and assigned to EASIC on July, 2010 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7759971	July 20, 2010
‌ US Patent 7550996 Structured integrated circuit device	Patent 7550996 was granted and assigned to EASIC on June, 2009 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	7550996	June 23, 2009
‌ US Patent 8504865 Dynamic phase alignment	Patent 8504865 was granted and assigned to EASIC on August, 2013 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	8504865	August 6, 2013
‌ US Patent 8848479 Multiple write during simultaneous memory access of a multi-port memory device	Patent 8848479 was granted and assigned to EASIC on September, 2014 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	8848479	September 30, 2014
‌ US Patent 8436700 MEMS-based switching	Patent 8436700 was granted and assigned to EASIC on May, 2013 by the United States Patent and Trademark Office.		EASIC	United States Patent and Trademark Office	8436700	May 7, 2013
‌ US Patent 8339844 Programmable vias for structured ASICs			EASIC	United States Patent and Trademark Office	8339844	December 25, 2012

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